View IS41C82052-60JI_5720694.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

integrated silicon solution, inc. 1-800-379-4774 1 rev. a 12/19/00 issi reserves the right to make changes to its products at any time without notice in order to improve design and supply the be st possible product. we assume no responsibility for any errors which may appear in this publication. ? copyright 2000, integrated silicon solution, inc. is41c82052 is41lv82052 issi ? features ? fast page mode access cycle ? ttl compatible inputs and outputs ? refresh interval: -- 2,048 cycles/32 ms ? refresh mode: ras -only, cas -before- ras (cbr), and hidden ? single power supply: 5v10% or 3.3v 10% ? byte write and byte read operation via two cas ? industrial temperature range -40c to 85c description the issi is41c82052 and is41lv82052 are 2,097,152 x 8-bit high-performance cmos dynamic random access memory. the fast page mode allows 2,048 random accesses within a single row with access cycle time as short as 20 ns per 4-bit word. these features make the is41c82052 and is41lv82052 ideally suited for hi gh-bandwidth graphics, digital signal processing, high-performance computing systems, and peripheral applications. the is41c82052 and is41lv82052 are packaged in 28-pin 300-mil soj and 28-pin tsop (type ii) with jedec standard pinouts. 2m x 8 (16-mbit) dynamic ram with fast page mode november 2000 key timing parameters parameter -50 -60 unit ras access time (t rac )5060ns cas access time (t cac )1315ns column address access time (t aa ) 25 30 ns fast page mode cycle time (t pc ) 20 25 ns read/write cycle time (t rc ) 84 104 ns product series overview part no. refresh voltage is41c82052 2k 5v 10% is41lv82052 2k 3.3v 10% 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 vcc i/o0 i/o1 i/o2 i/o3 we ras nc a10 a0 a1 a2 a3 vcc gnd i/o7 i/o6 i/o5 i/o4 cas oe a9 a8 a7 a6 a5 a4 gnd pin descriptions a0-a10 address inputs i/o0-7 data inputs/outputs we write enable oe output enable ras row address strobe cas column address strobe vcc power gnd ground nc no connection pin configuration 28 pin soj, tsop (type ii)
2 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? functional block diagram oe we cas cas we oe data i/o bus column decoder sense amplifiers memory array 2,097,152 x 8 row decoder data i/o buffers cas control logic we control logic oe control logic i/o0-i/o7 ras ras a0-a10 ras clock generator refresh counter address buffers truth table function ras cas we oe address t r /t c i/o standby h h x x x high-z read l l h l row/col d out write: word (early write) l l l x row/col d in read-write l l h ll h row/col d out , d in hidden refresh read l h l l h l row/col d out write (1) l h l l l x row/col d out ras -only refresh l h x x row/na high-z cbr refresh h l l x x x high-z note: 1. early write only.
integrated silicon solution, inc. 1-800-379-4774 3 rev. a 12/19/00 is41c82052 is41lv82052 issi ? functional description the is41c82052 and is41lv82052 are cmos drams optimized for high-speed bandwidth, low power applications. during read or write cycles, each bit is uniquely addressed through the 11 address bits. these are entered 11 bits (a0-a10) at a time. the row address is latched by the row address strobe ( ras ). the column address is latched by the column address strobe ( cas ). ras is used to latch the first nine bits and cas is used the latter ten bits. memory cycle a memory cycle is initiated by bring ras low and it is terminated by returning both ras and cas high. to ensures proper device operation and data integrity any memory cycle, once initiated, must not be ended or aborted before the minimum t ras time has expired. a new cycle must not be initiated until the minimum precharge time t rp , t cp has elapsed. read cycle a read cycle is initiated by the falling edge of cas or oe , whichever occurs last, while holding we high. the column address must be held for a minimum time specified by t ar . data out becomes valid only when t rac , t aa , t cac and t oea are all satisfied. as a result, the access time is dependent on the timing relationships between these parameters. write cycle a write cycle is initiated by the falling edge of cas and we , whichever occurs last. the input data must be valid at or before the falling edge of cas or we , whichever occurs last. auto refresh cycle to retain data, 2,048 refresh cycles are required in each 32 ms period. there are two ways to refresh the memory: 1. by clocking each of the 2,048 row addresses (a0 through a10) with ras at least once every 32 ms. any read, write, read-modify-write o r ras-only cycle refreshes the addressed row. 2. using a cas -before- ras refresh cycle. cas -before- ras refresh is activated by the falling edge of ras , while holding cas low. in cas -before- ras refresh cycle, an internal 9-bit counter provides the row addresses and the external address inputs are ignored. cas -before- ras is a refresh-only mode and no data access or device selection is allowed. thus, the output remains in the high-z state during the cycle. power-on after application of the v cc supply, an initial pause of 200 s is required followed by a minimum of eight initialization cycles (any combination of cycles contain- ing a ras signal). during power-on, it is recommended that ras track with v cc or be held at a valid v ih to avoid current surges.
4 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? absolute maximum ratings (1) symbol parameters rating unit v t voltage on any pin relative to gnd 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 v cc supply voltage 5v C1.0 to +7.0 v 3.3v C0.5 to +4.6 i out output current 50 ma p d power dissipation 1 w t a commercial operation temperature 0 to +70 c industrial operation temperature -40 to +85 t stg storage temperature C55 to +125 c note: 1. stress greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. recommended operating conditions (voltages are referenced to gnd.) symbol parameter min. typ. max. unit v cc supply voltage 5v 4.5 5.0 5.5 v 3.3v 3.0 3.3 3.6 v ih input high voltage 5v 2.4 v cc + 1.0 v 3.3v 2.0 v cc + 0.3 v il input low voltage 5v C1.0 0.8 v 3.3v C0.3 0.8 t a commercial ambient temperature 0 70 c industrial ambient temperature -40 85 c capacitance (1,2) symbol parameter max. unit c in 1 input capacitance: a0-a10(a11) 5 pf c in 2 input capacitance: ras , cas , we , oe 7pf c io data input/output capacitance: i/o0-i/o3 7 pf notes: 1. tested initially and after any design or process changes that may affect these parameters. 2. test conditions: t a = 25c, f = 1 mhz.
integrated silicon solution, inc. 1-800-379-4774 5 rev. a 12/19/00 is41c82052 is41lv82052 issi ? electrical characteristics (1) (recommended operating conditions unless otherwise noted.) symbol parameter test condition v cc speed min. max. unit i il input leakage current any input 0v v in vcc C5 5 a other inputs not under test = 0v i io output leakage current output is disabled (hi-z) C5 5 a 0v v out vcc v oh output high voltage level i oh = C5.0 ma, vcc = 5v 2.4 v i oh = C2.0 ma, vcc = 3.3v v ol output low voltage level i ol = 4.2 ma, vcc = 5v 0.4 v i ol = 2 ma, vcc = 3.3v i cc 1 standby current: ttl ras , cas v ih commercial 5v 2 ma 3.3v 0.5 industrial 5v 3 3.3v 2 i cc 2 standby current: cmos ras , cas v cc C 0.2v 5v 1 ma 3.3v 0.5 i cc 3 operating current: ras , cas , -50 120 ma random read/write (2,3) address cycling, t rc = t rc (min.) -60 110 average power supply current i cc 4 operating current: ras = v il , cas v ih -50 90 ma fast page mode (2,3,4) t rc = t rc (min.) -60 80 average power supply current i cc 5 refresh current: ras cycling, cas v ih -50 120 ma ras -only (2,3) t rc = t rc (min.) -60 110 average power supply current i cc 6 refresh current: ras , cas cycling -50 120 ma cbr (2,3,5) t rc = t rc (min.) -60 110 average power supply current notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycles ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. dependent on cycle rates. 3. specified values are obtained with minimum cycle time and the output open. 4. column-address is changed once each fast page cycle. 5. enables on-chip refresh and address counters.
6 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? ac characteristics (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t rc random read or write cycle time 84 104 ns t rac access time from ras (6, 7) 50 60 ns t cac access time from cas (6, 8, 15) 13 15 ns t aa access time from column-address (6) 25 30 ns t ras ras pulse width 50 10k 60 10k ns t rp ras precharge time 30 40 ns t cas cas pulse width (23) 8 10k 10 10k ns t cp cas precharge time (9) 9 9 ns t csh cas hold time (21) 38 40 ns t rcd ras to cas delay time (10, 20) 12 37 14 45 ns t asr row-address setup time 0 0 ns t rah row-address hold time 8 10 ns t asc column-address setup time (20) 0 0 ns t cah column-address hold time (20) 8 10 ns t ar column-address hold time 30 40 ns (referenced to ras ) t rad ras to column-address delay time (11) 10 25 12 30 ns t ral column-address to ras lead time 25 30 ns t rpc ras to cas precharge time 5 5 ns t rsh ras hold time 8 10 ns t rhcp ras hold time from cas precharge 30 35 ns t clz cas to output in low-z (15, 24) 0 0 ns t crp cas to ras precharge time (21) 5 5 ns t od output disable time (19, 24) 315 315 ns t oe output enable time (15, 16) 12 15 ns t oed output enable data delay (write) 12 15 ns t oehc oe high hold time from cas high 5 5 ns t oep oe high pulse width 10 10 ns t oes oe low to cas high setup time 5 5 ns t rcs read command setup time (17, 20) 0 0 ns t rrh read command hold time 0 0 ns (referenced to ras ) (12) t rch read command hold time 0 0 ns (referenced to cas ) (12, 17, 21) t wch write command hold time (17) 8 10 ns t wcr write command hold time 40 50 ns (referenced to ras ) (17) t wp write command pulse width (17) 8 10 ns t wpz we pulse widths to disable outputs 7 7 ns
integrated silicon solution, inc. 1-800-379-4774 7 rev. a 12/19/00 is41c82052 is41lv82052 issi ? ac characteristics (continued) (1,2,3,4,5,6) (recommended operating conditions unless otherwise noted.) -50 -60 symbol parameter min. max. min. max. units t rwl write command to ras lead time (17) 13 15 ns t cwl write command to cas lead time (17, 21) 8 10 ns t wcs write command setup time (14, 17, 20) 0 0 ns t dhr data-in hold time (referenced to ras )39 39 ns t ach column-address setup time to cas 15 15 ns precharge during write cycle t oeh oe hold time from we during 8 10 ns read-modify-write cycle (18) t ds data-in setup time (15, 22) 0 0 ns t dh data-in hold time (15, 22) 8 10 ns t rwc read-modify-write cycle time 108 133 ns t rwd ras to we delay time during 64 77 ns read-modify-write cycle (14) t cwd cas to we delay time (14, 20) 26 32 ns t awd column-address to we delay time (14) 39 47 ns t pc fast page mode read or write 20 25 ns cycle time t rasp ras pulse width 50 100k 60 100k ns t cpa access time from cas precharge (15) 30 35 ns t prwc read-write cycle time (24) 56 68 ns t coh data output hold after cas low 5 5 ns t off output buffer turn-off delay from 0 12 0 15 ns cas or ras (13,15,19, 24) t whz output disable delay from we 310 310 ns t csr cas setup time (cbr refresh) (20, 25) 5 5 ns t chr cas hold time (cbr refresh) ( 21, 25) 8 10 ns t ord oe setup time prior to ras during 0 0 ns hidden refresh cycle t ref auto refresh period 2,048 cycles 32 32 ms t t transition time (rise or fall) (2, 3) 150 150 ns ac test conditions output load: two ttl loads and 50 pf (vcc = 5.0v 10%) one ttl load and 50 pf (vcc = 3.3v 10%) input timing reference levels: v ih = 2.4v, v il = 0.8v (vcc = 5.0v 10%); v ih = 2.0v, v il = 0.8v (vcc = 3.3v 10%) output timing reference levels: v oh = 2.0v, v ol = 0.8v (vcc = 5v 10%, 3.3v 10%)
8 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? notes: 1. an initial pause of 200 s is required after power-up followed by eight ras refresh cycle ( ras -only or cbr) before proper device operation is assured. the eight ras cycles wake-up should be repeated any time the t ref refresh requirement is exceeded. 2. v ih (min) and v il (max) are reference levels for measuring timing of input signals. transition times, are measured between v ih and v il (or between v il and v ih ) and assume to be 1 ns for all inputs. 3. in addition to meeting the transition rate specification, all input signals must transit between v ih and v il (or between v il and v ih ) in a monotonic manner. 4. if cas and ras = v ih , data output is high-z. 5. if cas = v il , data output may contain data from the last valid read cycle. 6. measured with a load equivalent to one ttl gate and 50 pf. 7. assumes that t rcd - t rcd (max). if t rcd is greater than the maximum recommended value shown in this table, t rac will increase by the amount that t rcd exceeds the value shown. 8. assumes that t rcd ? t rcd (max). 9. if cas is low at the falling edge of ras , data out will be maintained from the previous cycle. to initiate a new cycle and clear the data output buffer, cas and ras must be pulsed for t cp . 10. operation with the t rcd (max) limit ensures that t rac (max) can be met. t rcd (max) is specified as a reference point only; if t rcd is greater than the specified t rcd (max) limit, access time is controlled exclusively by t cac . 11. operation within the t rad (max) limit ensures that t rcd (max) can be met. t rad (max) is specified as a reference point only; if t rad is greater than the specified t rad (max) limit, access time is controlled exclusively by t aa . 12. either t rch or t rrh must be satisfied for a read cycle. 13. t off (max) defines the time at which the output achieves the open circuit condition; it is not a reference to v oh or v ol . 14. t wcs , t rwd , t awd and t cwd are restrictive operating parameters in late write and read-modify-write cycle only. if t wcs ? t wcs (min), the cycle is an early write cycle and the data output will remain open circuit throughout the entire cycle. if t rwd ? t rwd (min), t awd ? t awd (min) and t cwd ? t cwd (min), the cycle is a read-write cycle and the data output will contain data read from the selected cell. if neither of the above conditions is met, the state of i/o (at access time and until cas and ras or oe go back to v ih ) is indeterminate. oe held high and we taken low after cas goes low result in a late write ( oe -controlled) cycle. 15. output parameter (i/o) is referenced to corresponding cas input. 16. during a read cycle, if oe is low then taken high before cas goes high, i/o goes open. if oe is tied permanently low, a late write or read-modify-write is not possible. 17. write command is defined as we going low. 18. late write and read-modify-write cycles must have both t od and t oeh met ( oe high during write cycle) in order to ensure that the output buffers will be open during the write cycle. the i/os will provide the previously written data if cas remains low and oe is taken back to low after t oeh is met. 19. the i/os are in open during read cycles once t od or t off occur. 20. determined by falling edge of cas . 21. determined by rising edge of cas . 22. these parameters are referenced to cas leading edge in early write cycles and we leading edge in late write or read-modify-write cycles. 23. cas must meet minimum pulse width. 24. the 3 ns minimum is a parameter guaranteed by design. 25. enables on-chip refresh and address counters.
integrated silicon solution, inc. 1-800-379-4774 9 rev. a 12/19/00 is41c82052 is41lv82052 issi ? read cycle t ras t rc t rp t ar t cah t asc t rad t ral oe i/o we address cas ras row column open open valid data t csh t cas t rsh t crp t clch t rcd t rah t asr t rrh t rch t rcs t aa t cac t off (1) t rac t clc t oes t oe t od row dont care note: 1. t off is referenced from rising edge of ras or cas , whichever occurs last.
10 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? read write cycle (late write and read-modify-write cycles) t ras t rwc t rp t ar t cah t asc t rad t ral t ach we oe address cas ras row column t csh t cas t rsh t crp t clch t rcd t rah t asr t rwd t cwl t cwd t rwl t awd t wp t rcs t cac t clz t ds t dh t oeh t od t oe t rac t aa i/o open open valid d out valid d in row dont care
integrated silicon solution, inc. 1-800-379-4774 11 rev. a 12/19/00 is41c82052 is41lv82052 issi ? early write cycle ( oe = don't care) t ras t rc t rp t ar t cah t asc t rad t ral t ach i/o we address cas ras row column t csh t cas t rsh t crp t clch t rcd t rah t asr t cwl t wcr t wch t rwl t wp t wcs t dh t ds t dhr valid data row dont care
12 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? fast-page-mode read cycle out t ar i/o we oe address cas ras row column column column t ar t csh t cas t cas t cas t rasp t rsh t prwc t rcd t crp t asr t rad t rcs t asc t asc t asc t ral t cah t cp t cp t rp t cah t cac t aa t clz t rac t oe t clz t cac t oe t cac t oe out out t oed t oed t oed t clz t aa t aa t rah t cpwd t cpwd t cah t crp
integrated silicon solution, inc. 1-800-379-4774 13 rev. a 12/19/00 is41c82052 is41lv82052 issi ? fast-page-mode read write cycle (late write and read-modify-write cycles) out t ar t rwd t awd i/o we oe address cas ras row column column column t ar t csh t cas t cas t cas t rasp t rsh t prwc t rcd t cwd t cwd t cwd t crp t asr t rad t rcs t asc t asc t asc t ral t cah t cp t cp t rp t cah t awd t awd t cac t aa t dh t clz t rac t dh t dh t oea t clz t cac t oea t cac t oea out out in in in t oez t oez t oed t oed t ds t oez t oed t ds t clz t aa t aa t wp t rah t wp t wp t cwl t cwl t cwl t rwl t cpwd t cpwd t cah t crp t ds dont care
14 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? fast page mode early write cycle t ar i/o we oe address cas ras row column column column t ar t cwl t wcr t dhr t csh t cas t cas t cas t rasp t rsh t rhcp t pc t rcd t crp t asr t wcs t ds t rad t asc t asc t asc t ral t cah t wch t dh t ds t ds t dh t dh t cp t cp t rp t cah t rah t cah t crp t cwl t wcs t wcs t wch t wp t wp t cwl t wch t wp valid d in valid d in valid d in dont care
integrated silicon solution, inc. 1-800-379-4774 15 rev. a 12/19/00 is41c82052 is41lv82052 issi ? ras -only refresh cycle ( oe , we = don't care) t ras t rc t rp i/o address cas ras row open t crp t rah t asr t rpc row dont care
16 integrated silicon solution, inc. 1-800-379-4774 rev. a 12/19/00 is41c82052 is41lv82052 issi ? hidden refresh cycle (1) ( we = high; oe = low) cbr refresh cycle (addresses; we , oe = don't care) t ras t ras t rp t rp i/o cas ras open t cp t rpc t csr t chr t rpc t csr t chr t ras t ras t rp cas ras t crp t rcd t rsh t chr t ar t asc t rad address row column t rah t asr t ral t cah i/o open open valid data t aa t cac t rac t clz t off (2) oe t oe t ord t od dont care dont care
integrated silicon solution, inc. 1-800-379-4774 17 rev. a 12/19/00 is41c82052 is41lv82052 issi ? ordering information industrial range: -40 c to 85c voltage: 5v speed (ns)order part no. package 50 is41c82052-50ji 300-mil soj 50 is41c82052-50ti tsop (type ii) 60 IS41C82052-60JI 300-mil soj 60 is41c82052-60ti tsop (type ii) voltage: 3.3v speed (ns)order part no. package 50 is41lv82052-50ji 300-mil soj 50 is41lv82052-50ti tsop (type ii) 60 is41lv82052-60ji 300-mil soj 60 is41lv82052-60ti tsop (type ii) issi ? integrated silicon solution, inc. 2231 lawson lane santa clara, ca 95054 tel: 1-800-379-4774 fax: (408) 588-0806 e-mail: sales@issi.com www.issi.com ordering information commercial range: 0 c to 70 c voltage: 5v speed (ns)order part no. package 50 is41c82052-50j 300-mil soj 50 is41c82052-50t tsop ( type ii) 60 is41c82052-60j 300-mil soj 60 is41c82052-60t tsop ( type ii) voltage: 3.3v speed (ns)order part no. package 50 is41lv82052-50j 300-mil soj 50 is41lv82052-50t tsop ( type ii) 60 is41lv82052-60j 300-mil soj 60 is41lv82052-60t tsop ( type ii)

▲Up To Search▲

Price & Availability of IS41C82052-60JI

	To Download IS41C82052-60JI Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .